发明名称 |
Boost clock circuit for driving redundant wordlines and sample wordlines |
摘要 |
A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator. |
申请公布号 |
US4922128(A) |
申请公布日期 |
1990.05.01 |
申请号 |
US19890296995 |
申请日期 |
1989.01.13 |
申请人 |
IBM CORPORATION |
发明人 |
DHONG, SANG H.;HWANG, WEI;LU, NICKY C. |
分类号 |
G11C11/407;G11C8/18;G11C29/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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