发明名称 |
Gate array device having a memory cell/interconnection region |
摘要 |
A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
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申请公布号 |
US4922441(A) |
申请公布日期 |
1990.05.01 |
申请号 |
US19880143715 |
申请日期 |
1988.01.14 |
申请人 |
RICOH COMPANY, LTD. |
发明人 |
TSUKAGOSHI, TOSHIHIRO;FUKUSHIMA, MASANOBU;YOSHIOKA, KEIICHI;YASUI, TAKASHI |
分类号 |
G11C11/412;G11C17/12;H01L27/11;H01L27/118;H03K19/173;(IPC1-7):G06F15/60 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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