| 摘要 |
PURPOSE:To reduce the required number of elements by constituting one bit of a shift register of four elements in total, a transmission gate element, two clocked inverter elements, and an inverter element by using incidental capacitance positively. CONSTITUTION:A first clocked inverter 10 is interposed between the input of a latch circuit consisting of an inverter 11 and a second clocked inverter 12, and a transmission gate 9. Data held at the incidental capacitance 15 on the input side of the first clocked inverter 10 in a first state i.e. a state where the on-states of the transmission gate 9 and the second clocked inverter 12 and the off-state of the first clocked inverter 10 are set is transmitted to a succeeding stage in a second state where the off-states of the transmission gate 9 and the second clocked inverter 12 and the on-state of the first clocked inverter 10 are set, then, the data inputted to the transmission gate 9 is shifted. In such a way, it is possible to reduce the number of elements required for the constitution of the shift register of one bit. |
