发明名称 MULTIPLIER
摘要 PURPOSE:To simplify and miniaturize a multiplexer by multiplying plural multiplication coefficients whose minimum weight are displayed decided in advance by input data by controlling a selector, an inverter, and the carry input of an adder. CONSTITUTION:The selector 200 selects the left shift data of multiplication input corresponding to a term coefficient which becomes the most significant non-zero of the multiplication coefficient, and the selectors 201 and 202 select the left shift data of respective multiplication input corresponding to the term coefficients which become the non-zeros of residual multiplication coefficients by a selection signal SEL, respectively. The inverters 203 and 204 execute the bit inversion of data when the complement control signals IVT(1) and IVT(2) of 2 go to 1s when the term coefficients of the multiplication coefficients to which the selectors 201 and 202 correspond are set at -1. The arithmetic operation of the complement of 2 is performed by inputting 1 to the carry input(CI) of the adders 205 and 206. The adders 205 and 206 execute the multiplication of multiplication input data X by the absolute value of the multiplication coefficient after adding the output data of the selector 200 on that of the inverters 203 and 204.
申请公布号 JPH02115929(A) 申请公布日期 1990.04.27
申请号 JP19880269732 申请日期 1988.10.25
申请人 NEC CORP 发明人 MIYAZAKI TAKASHI
分类号 G06F7/533;G06F7/487;G06F7/49;G06F7/508;G06F7/52 主分类号 G06F7/533
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