Central processor condition code method and apparatus.

摘要

A method and apparatus is disclosed for control of a central processor in response to a branch instruction using two separate, subsequently updated condition codes. Computer architecture is provided wherein the condition codes which determine the processor state result from the execution of instructions prior to the currently executing instruction. When the preceding instructions are executed, condition codes are set and maintained in a first condition code register. The first condition code is transferred to the second condition code register, and the first condition code register is updated to reflect the result of the current instruction execution. Any condition code state such as a branch used by the third instruction is based on the condition code state maintained in the second condition code register. The processor is provided with code which compiled according to the present invention, provides improved processor performance by reducing delays in instruction execution. If the current instruction is a condition code dependant instruction such as a branch instruction, this third instruction will execute based on the condition code maintained in the second condition code register.