发明名称 |
Binary calculation circuit |
摘要 |
A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai(+)Bi) and its complement (Ai(+)Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai(+)Bi) is produced by inverting the two input bit exclusive-OR signal (Ai(+)Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai(+)Bi) and its complement (Ai(+)Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).
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申请公布号 |
US4920509(A) |
申请公布日期 |
1990.04.24 |
申请号 |
US19880167787 |
申请日期 |
1988.03.11 |
申请人 |
ETAT FRANCAIS, REPRESENTE PAR LE MINISTRES DELEGUE DES POSTES ET TELECOMMUNICATIONS (CENTRE NATIONAL D'ETUDES DES TELECOMMUNICATIONS) |
发明人 |
HMIDA, HEDI;DUHAMEL, PIERRE |
分类号 |
G06F7/501;G06F7/50;G06F7/503;G06F7/504;G06F7/506;G06F7/508 |
主分类号 |
G06F7/501 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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