| 摘要 |
<p>PURPOSE:To take an analytic processing by hardware dedicated to result analysis in parallel to simulation by including a memory control processor which stores an arithmetic result in a memory and reads a result out of the memory in parallel. CONSTITUTION:While binary result data outputted from a hardware simulator 105 are recorded on the memory, a memory control processor 106 reads the result out of the memory 107 at a read request from the result analytic hardware 108 and analyzes the result in parallel to the simulating processing. Result analytic processing hardware 108 outputs the input result data at specified time and when there is an output value (expected value) to be compared, result analysis is outputted to a file 110 and a CRT 111 simultaneously with matching processing. Thus, the result of the logical simulation is stored on the memory 107 controlled by a memory processor 106 to perform the logical simulation in parallel and the result analysis is carried out in the processing time only by conventional hardware simulator.</p> |
