| 摘要 |
<p>The described embodiments of the present invention provide a memory (41) layout using complementary bitlines connected to a single sense amplifier (44). Extending from the sense amplifier, bitlines (54-56, 58-60) which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells (40-1) extending away from the sense amplifier (44). The other complementary bitline loops back and is connected to a set of memory cells (40-3) extending back towards the sense amplifier. The first extension from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections (54, 60) of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections (56, 58) of the bitlines are laterally separated, a wordline (64) passing across each of the second sections addresses a single memory cell (40). Therefore an optimally compact cross-point memory array may be fabricated. Using the described techniques an optimally compact array (41) having improved signal to noise characteristic may be fabricated.</p> |
