| 摘要 |
The circuit includes a latch (10) latching the master station data (DM) by a control signal (CONT2), a signal generator (20) generating a synchronous signal utilizing a certain time slot which is determined by a control signal (CONT2), a combining circuit (30) combining the master station data, the synchronous signal, and data (Ds) from the slave station by a control signal (SEL), a P/S converter (40) converting the signal transmitted from the combining circuit and certain bit parallel data to serial data according to the clock signal, and a control circuit (50) transmitting control signals (CONT1, CONT2, SEL, CLK) by accepting the control signal from a time sharing multicommunication system.
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