| 摘要 |
PURPOSE:To easily conduct a scan test and to adjust the delay time among circuit blocks by providing a data selector which selects data outputted from a delay circuit in normal operation. CONSTITUTION:In the normal operation, the outputs of circuit blocks 35-37 are inputted to delay circuits 40-48 and then inputted to following-stage blocks 35-37 through data selectors 26-34. For example, when 'HLHL' is inputted to transistors (TR) 84-87, it is considered that capacitors 92 and 94 are connected between a signal and the ground, and the signal can be delayed by a delay time corresponding to load capacity. Consequently, the delay time among the circuit blocks 35-37 in the normal operation can be controlled and adjusted externally by a delay control means (delay control terminals 70-78, etc.). |
