| 摘要 |
<p>PURPOSE:To decrease an output offset voltage by devising the circuit such that a difference between a base-emitter voltage of 1st and 5th transistors(TRs) and the base-emitter voltage of 4th and 6th TRs and a difference between the base-emitter voltage of 2nd TR and the base-emitter voltage of a 3rd TR are cancelled with each other. CONSTITUTION:While a rectangular wave signal supplied to a terminal 20 is at a VCC level, a capacitor Ca is discharged by a current IOSC and the capacitor Ca is charged by the current IOSC while the rectangular wave signal supplied to the terminal 20 is at a ground level. This is caused because a difference between a base-emitter voltage of TR Q1 and the base-emitter voltage of a TR Q5 and a difference between the base-emitter voltage of a TR Q7 and the base-emitter voltage of a TR Q8 are cancelled with each other. Thus, it is possible to decrease the production of an offset voltage.</p> |
