Synchronous sampling system.

摘要

The pixel clock of a system for receiving, sampling, and digitally storing the information contained in an analog sampled-data video signal is automatically synchronized and stabilized so that the received data is sampled by said system at or near the center of each successive received pixel period. A preset counter is employed to determine whether the receiving system clock is running at a predetermined number of pixel periods per horizontal sweep; any variation from the predetermined number is sensed and converted to a DC voltage level which is used to adjust the receiving system clock automatically to the correct number of periods per sweep. Synchronization of the receiving system clock is accomplished by triggering it with the sync pulse portions of the received video signal.