Semiconductor device having a stress relieving mechanism

摘要

PCT No. PCT/JP95/00714 Sec. 371 Date Mar. 19, 1997 Sec. 102(e) Date Mar. 19, 1997 PCT Filed Apr. 12, 1995 PCT Pub. No. WO96/09645 PCT Pub. Date Mar. 28, 1996A semiconductor device has a multi-layered wiring structure having a conductor layer to be electrically connected to a packaging substrate, the structure being provided on a circuit formation surface of a semiconductor chip; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate, after packaging thereof, and multiple wiring layers. In this semiconductor device, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase the signal speed; the distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in the improved connection reliability; and the number of terminals per unit is increased because of elimination of wire bonding.