发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To attain the sure phase locked loop establishment by alternately crossing the frequency pull-in range from upward or from downward with a bias voltage at the time of turning on the power source and at the time of changing the set frequency. CONSTITUTION:When the power source is turned on or when a set frequency fS of a frequency setter 15 is largely changed, the phase locked loop is instantaneously or naturally out. In the condition, a microprocessor 23 sends a frequency setting command (h) to a voltage width preparing means 21a of a bias voltage generating part 22. At such a time, after a time t0, a bias voltage VB is impressed from a bias voltage generating part 22 through a voltage adder 5 to a VCO 8 as a control voltage VC. Consequently, after a time t1 when the bias voltage VB exceeds a lower limit voltage V2 of the frequency pull-in range, the phase locked loop is established and a frequency f0 of an output signal (c) is controlled to a set frequency fS. Thus, when the bias voltage VB crosses a frequency pull-in range (V2 to V3) from downward or from downward, the chance to execute the phase locked loop establishment is given.
申请公布号 JPH0292115(A) 申请公布日期 1990.03.30
申请号 JP19880244846 申请日期 1988.09.29
申请人 ANRITSU CORP 发明人 IGAWA TETSUO;ORII EIJI
分类号 H03L7/187 主分类号 H03L7/187
代理机构 代理人
主权项
地址