发明名称 PLL CIRCUIT
摘要 PURPOSE:To reduce time till locking by supplying a reference voltage in response to a channel data outputted from a reference voltage generator to a VCO as an initial voltage. CONSTITUTION:A reference voltage corresponding to a channel data from a data input terminal is fed to a VCO 3 as an initial voltage via a switch 6 turned off after the elapse of a prescribed time from a reference voltage generator 7 storing the reference voltage in response to a channel data whose output impedance is lower than an LPF 4. Thus, the time till a PLL circuit is locked is shortened and the power supply is turned off when not required and the power supply is turned on as required to make the circuit stable quickly, and the PLL circuit can select the cut-off of the LPF without limitation of the lock time.
申请公布号 JPH0287719(A) 申请公布日期 1990.03.28
申请号 JP19880238946 申请日期 1988.09.26
申请人 NEC CORP 发明人 MIYAZAKI SHINICHI
分类号 H03L7/187 主分类号 H03L7/187
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