System for reexecuting branch instruction without fetching by storing target instruction control information

摘要

The present invention relates to a pipeline data processing apparatus wherein an instruction is fetched from a main storage, the instruction is decoded to generate control information for executing the instruction, and the control information is transferred to an instruction execute circuit. The target address of a branch instruction is stored in the index field of an associative memory, and control information obtained by decoding a target instruction of branch corresponding to the branch instruction is stored in the data field of the associative memory beforehand. When executing the branch instruction, the associative memory is accessed with the target address, and the control information of the corresponding entry is read out and is transferred to the instruction execute circuit, whereupon the instruction execute circuit starts executing the target instruction of branch instruction in succeession to the execution of the branch instruction.