| 摘要 |
<p>Apparatus for recognizing a logical status change between two values in a channel of an n-bit multiplex signal, incorporates and n-bit shift register controlled by the multiplex clock, and an AND gate connected to receive said input multiplex signal and an output of said shift register, with an inverter in series with one of the inputs of the AND gate. The AND gate produces a signal corresponding to a status change in a channel of the n-bit multiplex signal between two successive frames. A D-type flip-flop synchronizes the output of the AND gate with the multiplex clock.</p> |
