发明名称 FRAME SYNCHRONIZATION DETECTING CIRCUIT
摘要 PURPOSE:To suppress the increase of the number of a frames required till the frame synchronization is established by providing plural frame synchronization establishing circuits each consisting of a synchronizing word detection circuit and a frame synchronization discrimination circuit in pairs and deviating the operating start time of each properly. CONSTITUTION:A comparator 1 receiving a reception data detects a synchronizing word pattern in existence in the data and generates a coincidence pulse 3 in 1 bit data width. A frame synchronization discrimination circuit 15 receiving a synchronizing word pulse 11 sends a synchronizing word detection pulse 17 to a synchronization establishment control circuit 21 and reaches the standby state for a synchronizing word pulse to be reached after one frame. A coincidence pulse 4 from a comparator 2 passes through an AND gate 10 to be a synchronizing word pulse 12, which is sent to a frame synchronizing discrimination circuit 18. The frame synchronizing discrimination circuit 16 receiving the synchronizing word pulse 12 sends a synchronizing word detection pulse 18 to the synchronization establishment control circuit 21 and reaches the standby state for the synchronizing word 12 to be reached after one frame.
申请公布号 JPH0282828(A) 申请公布日期 1990.03.23
申请号 JP19880233683 申请日期 1988.09.20
申请人 NEC CORP 发明人 OI TOMOYUKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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