发明名称 COUNTER CHECK SYSTEM
摘要 PURPOSE:To easily detect a fault in the stepping of a counter only through the addition of a simple hardware by discriminating the counter to be faulty when a detection means confirms that an output of a circuit latching parity is unchanged with the stepping of the counter. CONSTITUTION:A counter 1 in figure is operated so that the count is stepped every time an advance condition signal 10 is 'ON' (same definition as 'present'). An output signal 15 of a parity latch circuit 3 is compared with an output signal (count) 12 of the counter 1 by a parity check circuit 4, which generates a parity error output signal 13 if the parity is dissident. Moreover, a parity change detection circuit 5 has a function storing the output signal 15 of the parity latch circuit 3 depending on the preceding count and compares the parity of a new parity output signal 15 of the parity latch circuit 3 revised with the stepping condition signal 10 set to 'ON' with the stored parity by the preceding count to detect the coincidence.
申请公布号 JPH0282815(A) 申请公布日期 1990.03.23
申请号 JP19880233597 申请日期 1988.09.20
申请人 FUJITSU LTD 发明人 TAKAHASHI HIROSHI
分类号 H03K21/40 主分类号 H03K21/40
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