| 摘要 |
PURPOSE: To initialize only a required part by inhibiting the propagation operation of an initialization operation from one of plural processor latch groups for which a processor latch is divided to a succeeding processor latch group based on the kind of initialization conditions. CONSTITUTION: A shift clock A (SCL A) is connected to the master latches of the shift register latches SRL1-SRLn, SRL1-SRLt and SRL1-RLv of respective reset areas F, I and S. For instance, when only the reset area F is to be reset, the combination '01' of SIF reset bits is supplied to a line 24 and sent to an AND gate 30. The output signal of the AND gate 30 is binary zero in any cases, and just when the code conditions for the AND gate 31 are satisfied, the shift clock A is transferred only to the master latch of the area F through the line 22a and propagation exceeding the area F becomes impossible. Thus, only the required part is initialized. |
