发明名称 PLL CIRCUIT
摘要 PURPOSE:To remarkably reduce jitter in phase locking by appling feedback from a voltage follower to a low-pass filter by only one resistor. CONSTITUTION:A phase comparator 1 compares the frequency and the phase of signal input 23 supplied from the outside with that of comparison output 24 in which the oscillation output of a VCO 5 is frequency-divided by a frequency divider 6, and a charge pump 2 turns on either a P-channel transistor 13 or an N-channel transistor 14 when no coincidence is obtained between the signal input 23 and the comparison output 24, then, supplies an electric charge to the low-pass filter. The output 26 of the low-pass filter is buffered by the voltage follower 4, and the output of the voltage follower 4 is fed back to the node 21 of the low-pass filter via the resistor 10. When the charge pump is activated in the phase locking, negative feedback by the response time of the voltage follower is applied on the low-pass filter, which functions to suppress the fluctuation of the potential of the output of the low-pass filter, thereby, the fluctuation of the input voltage of the VCO 5 can be reduced, and the jitter can be reduced.
申请公布号 JPH0267008(A) 申请公布日期 1990.03.07
申请号 JP19880219117 申请日期 1988.09.01
申请人 SEIKO EPSON CORP 发明人 IMAMURA YOICHI
分类号 H03L7/093 主分类号 H03L7/093
代理机构 代理人
主权项
地址