发明名称 DATA PROCESSOR
摘要 PURPOSE:To perform a series of arithmetic actions at a high speed by adding plural computing elements connected to a shared bus to an instruction executing means and supplying data again through an exclusive register which stores the arithmetic result with no intervention of the shared bus. CONSTITUTION:A barrel shifter 16 transfers the arithmetic subject data and the arithmetic result data via the internal buses BUS1, BUS2 and BUS3 serving as the shared buses, receives the arithmetic subject data with no intervention of those internal buses and also stores the arithmetic result data. In other words, the exclusive registers 28 and 29 are prepared for the shifter 16. The output terminal of the register 28 is connected to the BUS1 as well as to the input terminal of a selector 22. The output terminal of this selector 22 is connected to one of two input terminals of the shifter 16. The output terminal of the register 29 is connected to the BUS2 as well as to the input terminal of a selector 24 whose output terminal is connected to the other input terminal of the shifter 16.
申请公布号 JPH0266624(A) 申请公布日期 1990.03.06
申请号 JP19880218821 申请日期 1988.09.01
申请人 HITACHI LTD 发明人 SATOMURA RYUICHI
分类号 G06F7/00;G06F9/30;G06F9/38 主分类号 G06F7/00
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