发明名称 LOGICAL CIRCUIT SIMULATION SYSTEM
摘要 PURPOSE:To extract the pass of data, in which an attention signal is propagated, by investigating how the attention signal is transmitted in a logical circuit with a given test pattern. CONSTITUTION:Logical circuit information to be composed of the information of a component, which constitutes the logical circuit, the information of connecting relation for the component and the information of a logical circuit describing language, etc., the information of a circuit pattern for the logical circuit to execute simulation, the information of an input test pattern 2 of a change information for an input signal, which is inputted to the circuit pattern, and the information of attention signal indication 3 to give attention to the change of the respective signals in the circuit when circuit operation is simulated and to designate the attention signal are inputted to an event processing part 4 and the simulation processing of the test pattern is executed. A processed result is outputted as an attention signal trace list 5, which wholly records related events, and a simulation result 6 to output the time change of respective signal values in the circuit pattern.
申请公布号 JPH0261771(A) 申请公布日期 1990.03.01
申请号 JP19880212509 申请日期 1988.08.29
申请人 TOSHIBA CORP 发明人 TAKEI TSUTOMU
分类号 G01R31/28;G06F17/50;G06F19/00 主分类号 G01R31/28
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