| 摘要 |
PURPOSE:To reduce effect of a skew of a clock by a connection between flip flops through a delay means. CONSTITUTION:Outputs of D flip flops (FF) 11, 12 and 13 are connected to inputs of FFs at the next stage through inverters I1, I2 and I3. Now, it is assumed that a skew exists only for t1-2 between clock signals CK1 and CK2 at the inputs. Time is represented by tdQ from the inputting of clocks of the FFs to the outputting of a data, a delay time with inverters by tdI and a setup time of the FFs by ts. Then, the delay tdI is made larger enough than the skew t1-2 while being selected to be smaller enough than a cycle time of a serial shift register to set t1-2<tdQ+ts+tdI. Thus, the transfer of a data is accomplished normally regardless of any skew of the clock. |
