| 发明名称 |
SEMICONDUCTOR DEVICE COMPRISING A LOGIC CIRCUIT AND A MEMORY |
| 摘要 |
A semiconductor device comprises a logic circuit (132) and a memory (12) including a timing signal generator circuit, both formed on a substrate (11), and a wiring connecting the logic circuit (132) to the memory (12), in which a diffusion layer-fixed potential zone (15) to which a predetermined potential is applied is formed under an area of the wiring which is situated between the logic circuit (132) and the memory (12) whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation. |
| 申请公布号 |
EP0329100(A3) |
申请公布日期 |
1990.02.28 |
| 申请号 |
EP19890102574 |
申请日期 |
1989.02.15 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA;TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION |
发明人 |
SHIROTORI, TSUKASA C/O PATENT DIVISION;SAWADA, KAZUHIRO C/O PATENT DIVISION;SAKURAI, TAKAYASU C/O PATENT DIVISION |
| 分类号 |
H01L21/76;G11C11/401;H01L21/82;H01L21/822;H01L23/528;H01L27/04;H01L27/10;H01L27/105;H01L27/108;H01L27/118;(IPC1-7):H01L27/06;H01L23/52;H01L29/06 |
主分类号 |
H01L21/76 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
