发明名称 TIMING RECOVERY CIRCUIT
摘要 PURPOSE:To reflect the result of comparison onto the phase control of timing recovery by estimating a peak value of an impulse response from a reception signal from a line equalizer and calculating two mean values averaging the peak for a prescribed period with the self-running period inbetween and recognizing the direction of a frequency error from the comparison result. CONSTITUTION:When an initial pull-in end signal is given, a protection stage number counter 55 of a PLL circuit 5 advances a phase of a recovered clock by a prescribed phase quantity alpha, sends a peak h0(n) of the impulse response at a present point of time calculated by an impulse response arithmetic circuit 3 to an arithmetic result comparator 4 and an averaging section 41 calculates the mean value. When the averaging period is finished, an output of a NOR gate 46 goes to '1', the comparison of the comparator 43 is executed and the result is given to a protection stage number counter 55 of the PLL circuit 5 as a frequency error direction signal. The mean values are compared only once in such a manner to control the protection stage number in response to the frequency error direction.
申请公布号 JPH0254643(A) 申请公布日期 1990.02.23
申请号 JP19880206159 申请日期 1988.08.19
申请人 FUJITSU LTD 发明人 OTA SHINJI;FUKUDA SETSU
分类号 H03L7/06;H04L7/033;H04L7/10 主分类号 H03L7/06
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