| 摘要 |
PURPOSE:To test a digital signal processor with no extra circuit added to the processor by forming a 1st storage circuit with the 3rd and 4th storage means, storing the input signal data in time division into the 3rd and 4th means and then reading out these stored data. CONSTITUTION:A 1st storage circuit 220 of a digital signal processor DSP consists of the 3rd and 4th storage means 270 and 280. The input test signal data are stored in time division into both means 270 and 280 via a selection circuit 210. Then the data read out of the means 270 and 280 of the circuit 220 are read out to a 2nd storage circuit 230 and processed by a decoder DEC 240, tested. Then the data read via an external memory data bus are written in time division into a higher rank IRU 27 and a lower rank IRL 28 via a selection circuit SEL 21 which is switched to the test side. The address of an IR 23 is obtained from the data stored temporarily in the IRU 27 and the IRL 28, and a control signal is outputted via the DEC 24. |
