Adder circuit using 5211 code

摘要

The adder circuit according to the subject of the invention is not a standard adder circuit but a special adder circuit, which firstly has a dual full adder (7) to process the value 5, and secondly has one dual full adder each to process the values 1 and 2. If a carry with the value 4 occurs in the dual full adder (6), which processes the value 2, and this should be processed in the dual full adder (7), the remaining sum must be reduced by the number 1, so that a wrong sum is not formed. Circuit (2) is arranged for this reduction of the remaining sum by the digit 1. It is triggered simultaneously with high potential, and thus reduces its remaining sum value by the digit 1, because the negating circuit (74) is then at a low potential at its output. <IMAGE>