| 摘要 |
<p>A microcomputer comprising an instruction buffer receiving an instruction, a first decoder for decoding the instruction ouputted from instruction buffer so as to generate a write request detection signal, an instruction memory for receiving and storing the instruction outputted from instruction buffer, a program counter for indicating an address to be written or read, a second instruction decoder for receiving an instruction code read from the instruction memory and for generating data and control signals including a halt signal, a data memory for storing the data from the second instruction decoder in response to a write signal from the second instruction decoder and for outputting data stored in the data memory in response to a read signal from the second instruction decoder, an address counter for receiving an address information from the second instruction decoder and for supplying an address to the data memory, a logic circuit connected to receive through a gate the halt signal from the second instruction decoder and for generating a halt indication signal to the program counter so as to inhibit an updating of the program counter, the logic circuit being also connected to receive the write request detection signal from the first instruction decoder and the write request decode signal from the second instruction decoder so that the halt signal from being prevented from being inputted through the gate when the write request detection signal and the write request decode signal are in a predetermined condition, and a pulse input circuit for receiving a clock pulse for defining a periodical operation and for outputting the clock pulse to the program counter.</p> |
