发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE: To obtain an output pulse signal that is delayed only by a desired delay time by generating a delay current pulse signal based on an input pulse signal and a delay control signal in each edge of the input pulse signal and adding both of them. CONSTITUTION: The 1st comparator 12 receives an input pulse signal and the 1st reference signal REF1 and outputs a corresponding pulse signal. The input pulse signal and the signal REF1 are also supplied to the input terminal of each opposite polarity of the 2nd and 3rd comparators 14 and 16. Output signals of the comparators 14 and 16 are inputted to a pulse shaping circuit 18 and shaped into a pulse signal that corresponds to each edge of the input pulse signal. An output signal of the circuit 18 is added to a pulse output signal of the comparator 12 and equally and effectively changes the inclination of previous and following edges of the pulse signal. As a result, the pulse signal is effectively delayed.
申请公布号 JPH0239720(A) 申请公布日期 1990.02.08
申请号 JP19890153575 申请日期 1989.06.15
申请人 TEKTRONIX INC 发明人 KURARENSU II KOOWAN;RONARUDO KEE KURISUTENSEN
分类号 H03K5/00;H03K5/13 主分类号 H03K5/00
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