发明名称 WIRING FORMING METHOD AND SEMICONDUCTOR DEVICE
摘要 PURPOSE:To shorten a forming time by connecting a CVD wiring once to a part of a wiring which is provided in a semiconductor device, leading out the wiring at a part other than said part, and forming another CVD wiring so as to avoid said connecting point. CONSTITUTION:Power source lines are arranged on the topmost layer of an ordinary LSI. The line comprises a wide wiring in comparison with signal lines at a lower layer so as to supply electric power stably. Even if a part of the lines are cut away, there is almost no effect on the operation of the LSI. A topmost layer wiring 18 is cut away. Then windows are opened 9 at two places of the wiring layer at the topmost layer. A part which is machined in such a shape is formed at every position where CVD wirings 5 are crossed. When the wirings are formed in this way, the CVD wirings 5 are not short- circuited to each other.
申请公布号 JPH0239552(A) 申请公布日期 1990.02.08
申请号 JP19880188403 申请日期 1988.07.29
申请人 HITACHI LTD 发明人 SHIMASE AKIRA;ITO FUMIKAZU;HARAICHI SATOSHI;HONGO MIKIO;TAKAHASHI TAKAHIKO;OKAMOTO YOSHIHIKO
分类号 G03F7/26;H01L21/768;H01L21/82;H01L23/522 主分类号 G03F7/26
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