发明名称 FORMING METHOD FOR PATTERN OF HYBRID INTEGRATED CIRCUIT
摘要 PURPOSE:To improve connecting reliability by so forming a conductor pattern formed to be soldered and containing as a main ingredient silver-palladium alloy of relatively high palladium content on a ceramic board as to cover the part of the pattern formed for wirings having relatively low palladium content. CONSTITUTION:A conductor pattern for wirings of silver-palladium (Pd-Ag) alloy containing 10-20% or preferably approx. 50% of palladium (Pd) is printed and formed on a ceramic board 1 made of alumina (Al2O3) by a screen printing method. Then, a conductor pattern 20 to be soldered of silver-palladium (Pd-Ag) containing 25% or more of palladium (Pd) such as approx. 30% is so printed and formed by a similar method as to cover the part of the pattern 10, and sintered at 800-900 deg.C. Thereafter, a glass material 30 made of SiO2 (32%)-PbO (42%)-B2O3 (5.5%)-ZnO(5%)-Al2O3 (6.5%)-CaO (9%) is so printed and formed by a screen printing method as to cover the conductor connection part, and sintered at 500-600 deg.C.
申请公布号 JPH0239588(A) 申请公布日期 1990.02.08
申请号 JP19880188148 申请日期 1988.07.29
申请人 FUJITSU LTD 发明人 TAKABAYASHI HIROYUKI;KUMAI TOSHIO;MURAKAMI MICHITERU
分类号 H05K3/34;H05K1/03;H05K1/09;H05K1/16;H05K3/12;H05K3/24;H05K3/28 主分类号 H05K3/34
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