ASYNCHRONOUS VS SYNCHRONOUS DIGITAL DATA MULTIPLEXER/ DIMULTIPLEXER HAVING ASYNCHRONOUS CLOCK REGENERATING FUNCTION

摘要

PURPOSE: To make it possible to use a common bit synchronizing speed deskew and an error correcting circuit for all channels by multiplexing data which are received at an asynchronous clock speed and transmitting them synchronously, and demultiplexing synchronous data to respective channels for transmission at an asynchronous clock speed. CONSTITUTION: Data of respective channels are received by series-parallel(S/P) converters 14a to 14n and converted into parallel data of 8-bit words. The parallel data bytes from the converters 14a to 14n are successively transferred to an input FIFO one eighth as fast as a serial input clock speed through lines 16a to 16n. Then (m) synchronous transmission FIFOs 22a to 22m are used and assigned to one synchronous transmission channel. Data regenerated from a parallel channel of a recording and reproducing device 106 are received in synchronism through all parallel lines 150a to 150m at the parallel clock speed of lines 105.