| 摘要 |
The hardware device for obtaining error information in a pipeline data processing system according to the invention comprises two separate means 70, 86 for memory storage of the first and second error signals generated by error detectors 60, 62, 64, 66 respectively associated with the stages 12, 14, 16, 18 of the pipeline. A first error signal memory means 70 consists of a set of one-bit memory cells 70a, 70b, 70c, 70d respectively allocated to the stages of the pipeline. The first error signal memory means makes it possible to define the stage of the pipeline at which an error is initially detected. A second error signal memory means 86 reacts to an error detection signal and receives the error analysis information from the last stage 18 of the pipeline.
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