发明名称 PHASED LOCKED OSCILLATION CIRCUIT
摘要 PURPOSE:To reduce a transient response at the time of switching a loop gain by delaying a switching timing when the output current value of a charge pump circuit is switched so as not to be superposed on a timing to generate a current pulse by the charge pump circuit. CONSTITUTION:At a loop gain switching delay circuit 8, a D flip-flop 9 is set by the input of data inputted next when a signal 2a goes to a high level, and the output signal 8a of the loop gain switching delay circuit 8 is set being delayed by two and half cycles of a clock inputted hereafter, and the output current value of the charge pump circuit 4 is reduced. The timing to set the output signal 8a does not coincide with that to output the current by the charge pump circuit 4. Thereby, the next charge pump output timing i.e., the peak value of the third charge pump output current pulse of a charge pump output signal 4a can be reduced.
申请公布号 JPH0232622(A) 申请公布日期 1990.02.02
申请号 JP19880181779 申请日期 1988.07.22
申请人 NEC CORP 发明人 OKADA YOSHIAKI
分类号 H03L7/093;H03L7/107 主分类号 H03L7/093
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