| 摘要 |
<p>PURPOSE:To easily detect a memory cell whose holding characteristic is defective by applying a second voltage of a prescribed level lower than a first voltage used for normal write at the time of write for test. CONSTITUTION:A gate voltage control circuit 2 is provided which applies the first voltage of a prescribed level to the gate of a memory cell 11 of an UV- EPROM 10 at the time of normal write and applies the second voltage of the prescribed level lower than the first voltage to said gate at the time of write for test in accordance with the output signal of a write mode selecting circuit 1. At the time of write for test, a transistor TR Q2 is turned on by a select signal SM and a voltage Vpp is divided by resistances R1 and R2 and is applied to the gate of the memory cell 11, and write for test is performed with a threshold voltage of a level lower than the threshold voltage for normal write. Thus, the UV-EPROM where the memory cell having a defective holding characteristic exists is detected and excluded.</p> |
