发明名称 |
A pipeline having an integral cache for computer processors. |
摘要 |
<p>A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.</p> |
申请公布号 |
EP0352633(A2) |
申请公布日期 |
1990.01.31 |
申请号 |
EP19890113324 |
申请日期 |
1989.07.20 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
WITEK, RICHARD T.;WILLIAMS, DOUGLAS D.;STANLEY, TIMOTHY J.;FENWICK, DAVID M.;BURNS, DOUGLAS J.;STAMM, REBECCA L.;HEYE, RICHARD |
分类号 |
G06F9/38;G06F12/08;G06F15/78;G06F17/16 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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