发明名称 METHOD FORMING WIRING OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To realize multilayered wiring having well covering upper-layer wiring and a high-yield and high-reliability upper- and lower-wiring connecting section by forming the lower-layer wiring after forming only a pedestal at the part proposed for forming the lower- and upper-layer wiring connecting section and forming a film of glass or organic compound of silicon as an inter-layer insulating film by an applying method. CONSTITUTION:After forming only a pedestal 102 at the part proposed for forming a lower- and upper-layer wiring connecting section on a semiconductor substrate 101 on which a semiconductor element is formed, the 2nd conductor is formed on the entire surface of the substrate followed by the formation of lower-layer wiring 103 formed by photoetching. After forming the wiring 103, a film of glass or an organic compound of silicon is formed as an inter-layer insulating film A 106 by an applying method and a through hole 108 is dug by photoetching at the part proposed to the lower- and upper-wiring layer connecting section. Then the 3rd conductor is formed and upper-layer wiring 109 is formed from the 3rd conductor by photoetching. The seat 104 for the through hole 108 is formed, for example, simultaneously with the formation of the lower wiring layer 103. In addition, the 2nd and 1st inter-layer insulating films 107 and 105 of silicon nitridized or silicon oxidized films are provided by an applying method on and below the inter-layer insulating film A 106.
申请公布号 JPH0230137(A) 申请公布日期 1990.01.31
申请号 JP19880181008 申请日期 1988.07.19
申请人 NEC CORP 发明人 MIZUSHIMA KAZUYUKI
分类号 H01L21/3205;H01L21/768;H01L23/522 主分类号 H01L21/3205
代理机构 代理人
主权项
地址