发明名称 DELAY ANALYSIS SYSTEM FOR CIRCUIT
摘要 PURPOSE:To permit specifying of an error circuit element in a short time by analyzing all circuit element in a route being decided as a delay time error and providing an error circuit element specifying means. CONSTITUTION:All net-work information related to an object circuit of a delay analysis and delay time information are stored at a circuit storing means 1, a delay time analyzing means 2 executes a route analysis of the object circuit based on an information read out from this and outputs its result. By this method, in an error circuit element specifying means 3, a route analysis part 3-1 stores respective circuit elements in each routes being decided as the delay time error, next, a circuit element specifying part 3-2 specifies the error circuit element therein and stores. And, its result is outputted by a result output part 3-3.
申请公布号 JPH0228569(A) 申请公布日期 1990.01.30
申请号 JP19880179753 申请日期 1988.07.19
申请人 NEC CORP 发明人 ASANO HIROKO
分类号 G01R27/28;G06F17/50;G06F19/00 主分类号 G01R27/28
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