| 摘要 |
PURPOSE:To make page-mode writing possible by applying a specific voltage across required transistors in accordance with the erasure and program modes. CONSTITUTION:When a selected word line 3 corresponding to a page to which the page mode is to be performed is set to a high voltage and 0V is supplied to a non-selected word line 4 and all bit lines 1 and 2 while source lines 5 and 6 are floated, a high voltage is applied across the control gates and drains of memory transistors (TR) Q1 and Q3, the control gates of which are connected with the word line 3, and a high electric field is generated between a floating gate and drain. As a result, electrons are injected from the drain toward the floating gate due to a tunnel effect and the threshold voltages of the TRs Q1 and Q3 rise. Accordingly, logic '1' is written and the selected TRs Q1 and Q3 are erased. Therefore, when a specific voltage which is opposite to the voltage applied at the time of erasure is applied across the control gates and drain areas of the TRs Q1 and Q3 and a low write inhibit voltage is applied across the gates and drain areas of other non-selected TRs Q2 and Q4, page- mode writing can be performed. |
