| 摘要 |
<p>A ranking circuit operable in real time to rank a set of periodically changing sample values, having a series of sequentially clocked storage registers (VRH, VR1-VRN) for sequentially storing the sample values, a series of corresponding first comparators (CV1-CVN) for comparing each sample stored to the incoming sample, a summer (PAL1) for summing the outputs of the first comparators to assign an initial rank to the incoming sample, a series of rank registers (RR1-RRN) for storing the initial rank value and a rank value corresponding to each sample in the sample registers (VR1-VRN), increment/decrement logic (ID1-IDN-1) for adjusting each rank in the respective rank registers (RR1-RRN) as each new sample is received, logic (CTT, RTH, RTN, ΣT) for effectively excluding a target sample from the ranking process, and logic (CT1-CTN) for outputting a sample value of selected rank during each clock cycle. Optional logic (Σ1-Σ9, C1, C2, R1, R2, PROM1, PROM2) for automatically adjusting the selected rank based on the relative amplitudes of the samples being ranked is also disclosed.</p> |
