| 摘要 |
PURPOSE:To speed reading operation and to prevent a decrease in rewriting level by arranging memory cells, dummy cells, sense amplifiers, etc., as prescribed. CONSTITUTION:Left and right data lines D1L and D2L, D1R and D2R, etc., divided by transmission gate MOSFETS Q'5 and Q'6 are provided with individual sense amplifiers SAL and SAR which are not common, and memory cells M-CEL and dummy cells D-CEL are driven. Those sense amplifiers SAL and SAR perform high-speed amplification by a large input voltage and capacity values of data lines D1L... divided by FETs Q'5 and Q'6 decrease; and the capacity of the memory cells M-CEL and a readout level by charge dispersion both increase and the load capacity of the sense amplifiers SAL and SAR is decreased to further speed up the amplifying operation. Further, the sense amplifiers SAL... and data lines D1L... are connected directly to perform high-speed reading operation and a bootstrap voltage is transmitted to the data lines D1L... to prevent a decrease in rewriting level. |
