| 摘要 |
PURPOSE: To speed up the access time of data retrieval from a device by dividing a buffer for receiving or storing data signals from the rows of the memory cells of an array to >=2 pieces of blocks. CONSTITUTION: A matrix address multiplexer 5 has a multiplexing matrix address bus 6 as output which is connected to each of the several DRAM devices 7. The DRAM devices 7 output data to a CPU via the a CPU data bus 10. Namely, the time multiplexing matrix signals are inputted to the device via the bus 6. A timing and control circuit 76 receives a RAS signal 8 and a CAS signal 9. A static buffer 72 consisting of sense amplifier cells generally executes parallel communication with a charge array 71 via a circuit line 75. This static buffer 72 is divided to two or more blocks in its function. The respective blocks have the blocks of the data from the different rows of the array. As a result,, the probability of the 'hit' of the cache is greatly increased and the access from the buffer is speeded up. |
