| 摘要 |
<p>PURPOSE:To shorten time from the detection of a phase difference till the settling by combining 4 clock signals and 4 delay circuits. CONSTITUTION:Two clock signals among 4 clock signals CLK1-CLK4 whose duty ratio is 50%, with equal period and whose phase is deviated sequentially by 1/4 period each are latched respectively by flip-flops(FF) 1, 2 and one clock signal among the 4 clock signals is selected by a selector 3 by the combination of the latched clock signal level. Then the clock signal is used to branch the input signal latched by the FF 4 into four ways, they are inputted respectively to 4 delay circuits 5-8, each delay circuit retards the input signal by a delay time corresponding to the phase difference between the reception side clock and the its own corresponding clock signal set in advance, and a selector 9 selects the output of one relevant delay circuit according to the combination of the output of the FF 1, 2. Thus, the constitution is simplified and the circuit is made stable in a short time.</p> |
