| 摘要 |
PURPOSE:To broadly reduce a data line charging/discharging current and to improve information holding time, an alpha rays resistant sift error property and an S/N by reducing a data line voltage amplitude on memory cell signal amplifying. CONSTITUTION:A memory cell array MA of a memory circuit consists of plural D0, the inverse of D0-Dn and the onverse of Dn, word lines W0-Wn and a memory cell MC. Besides, the plural word lines and the one of data lines are selected with X and Y decoders XD and YD, a signal read out of the memory cell MC is amplified with sense amplifiers SA0-SAn. Besides, while a data line precharging signal the inverse of phiP is 4V at a high electric potential, it becomes 1V at a data line precharging electric potential. Then, sense amplifier driving signals phiSF and the inverse of phiSn become 4V, the sense amplifier becomes an off condition, the inverse of phiP becomes a low electric potential and the word line is selected. Besides, the electric potential difference between the data lines is lowered to a value which is a little larger than the threshold voltage of an MOS-FET constituting the sense amplifier, the electric potential of the inner high electric potential of a memory cell signal is selected and pressure is raised with a terminal to which the MOS-FET for transfer gate is not connected. |
