| 摘要 |
<p>PURPOSE:To enable the micronization of a memory transistor, to facilitate the control of a manufacturing process, and to obtain a highly integrated EPROM of high reliability by a method wherein a selection gate is provided between two adjacent memory transistors, optionally selected out of two or more memory transistors which constitute a NAND cell. CONSTITUTION:A region with no diffusion layer is provided between two memory transistors inside a NAND cell, isolating n<+>-type layers 72 and 73 of a source and a drain diffusion layer from each other, and the above region serves as a channel region and a selection gate 8 is formed thereon through the intermediary of a gate insulating film 3 to compose a selection transistor. The selection gate 8 is buried between two memory transistors and provided partially overlapping control gates 61 and 62 on both the sides. Therefore, a mask, used for isolating a source and a drain diffusion layer from each other between two memory transistors, does not need to be accurate in size and positioning, so that a selection gate can be constituted by use of a small space originally subsisted between two memory transistors.</p> |
