| 摘要 |
PURPOSE:To increase an operation speed by reducing impurity concentration of a channel stopper region defining the surrounding of a memory cell compared with that defining the surrounding of a semiconductor element of a peripheral circuit and further reducing operation voltage applied to a data line connected to an operation region of the memory cell compared with that used by the peripheral circuit. CONSTITUTION:In the title semiconductor integrated circuit device wherein the respective surroundings of semiconductor elements forming peripheral circuits such as a memory cell M, in which a memory cell array MA is connected to an extending data line, and a decoder circuit, etc., are defined by a field insulating film 6 and channel stopper regions 4, 5, impurity concentration of the channel stopper region 4 that defines the surrounding of the memory cell M is reduced compared with impurity concentrations of the channel stopper regions 4, 5 that defines the surroundings of the semiconductor elements of the peripheral circuits, and further operation voltage applied to the data line is lower than operation voltages used in the peripheral circuits. Hereby, pn junction capacitor between the operation region of the memory cell and the channel stopper region defining the surrounding of the operation region of the memory cell is reduced to reduce the load capacity of the data line, thereby the operation speed being increased. |
