| 摘要 |
PURPOSE:To enhance the resistance to a soft error by a method wherein concentrations of N-wells where a transistor is formed are different from each other. CONSTITUTION:An insulating film 11 is deposited on a P-type silicon semiconductor substrate 10 of a 100 crystal face; the insulating film 11 only in a position used to form a PMOS element is removed selectively by a photoetching method; an opening part 12 is formed. In succession, an N<+>-type buried collector layer 13 is formed by vapor diffusion or solid diffusion of Sb or by ion implantation of As or Sb from the opening part 12. Then, the insulating film 11 is removed from the whole surface; after that, B<+> ions are implanted into the whole surface of o wafer; a first low-concentration buried P-region 9 for punchtrough prevention use is formed. Then, ions are implanted only into a position used to form a memory cell array by using the photoetching method; then, a second high- concentration buried P-region 8 is formed. Thereby, it is possible to obtain a semiconductor device whose resistance to a soft error is high. |
