发明名称 |
SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES |
摘要 |
<p>SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.</p> |
申请公布号 |
CA1264200(A) |
申请公布日期 |
1990.01.02 |
申请号 |
CA19860499281 |
申请日期 |
1986.01.09 |
申请人 |
UNISYS CORPORATION |
发明人 |
LOGSDON, GARY L.;SCHEEVEL, MARK R.;WINCHELL, MICHAEL A. |
分类号 |
G06F12/00;G06F9/44;G06F9/45;(IPC1-7):G06F9/44 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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