| 摘要 |
Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multistage network. Without prolonging the individual phase durations or adding any registers, the added domino logic network can have a propagation delay time corresponding to more than one phase of the PLA, and hence the network can have correspondingly more stages and more added data processing capability. |
